1. Field of the Invention
Embodiments of the invention relate generally to a reduction of pins required to utilize and to select a memory rank.
2. Description of the Related Art
Demands for memory capacity continue to increase in modern electronics. At the same time, size of circuitry is at an increased premium as devices which utilize memory circuitry continue to shrink. One solution as to how to increase memory capacity while minimizing the amount of space required in implementing memory circuitry has involved the development of dual inline memory modules (DIMMs). DIMM chips allow for placement of memory chips on both sides of a printed circuit board. In this manner, the amount of memory chips accessible by a device may be doubled while using the same sized printed circuit board.
A second solution as to how to increase memory capacity while minimizing the amount of space required in implementing memory circuitry has involved the development of memory stacking. Memory stacking involves placing memory dies on top of each other, while sharing a common printed circuit board. Typically, the dies are packaged together into a single memory chip. The memory dies in the memory chip are typically referred to by rank. That is, a memory chip containing two memory dies in a single package has two ranks of memory. Thus, a DIMM containing two memory chips, each containing two memory dies, has four ranks of memory. The total number of memory ranks in a memory circuit is referred to as the memory density of the memory circuit.
The stacked memory dies in the memory chip are individually connected to a memory substrate. The memory substrate typically utilizes solder balls, bond wires, or leads to connect to a printed circuit board for connection of the memory chip to the electronic device. These connections between the circuit board and the memory chip may be termed “pins”. Through these pins, a device may access a large group of memory dies while minimizing the amount of board space required to interface with the printed circuit board on which the memory dies reside.
The pins, e.g., a lead, such as a metal wire, enable the memory chips to transmit signals to and receive signals from the printed circuit board. When adding ranks of memory, traditionally a pin has been added to address the additional rank. This pin is commonly known as a chip select (CS). Thus, if a chip included two ranks of memory, two CS pins would be employed to access the ranks. Additionally, memory chips may include a plurality of ports. Multi-port memory is capable of supporting simultaneous access. In addition to allowing simultaneous reads and writes, multi-port memory may allow for access from varied bus width inputs. When adding ranks of memory that have multiple ports, traditionally multiple port select (PS) pins are typically added. Thus, if a chip included a single memory die with four ports, four PS pins would be employed to access the memory chip. Similarly, if a DIMM included four stacked multi-port memory dies, each with four ports per memory die, then 16 PS pins would be employed to access the memory chips.
In certain devices, input/output (I/O) pin counts are at a premium. In these devices, adding multiple CS or PS pins becomes very expensive as the density of a memory circuit increases. Similarly, there are devices which may have fixed pin requirements, but that require more memory capacity than that which may be delivered across a system utilizing a single pin-per-rank or a single pin-per-port configuration. Thus, there is a need for a multi-rank and multi-port memory which may be accessed by a reduced number of pins. Embodiments of the invention may be directed to one or more of the problems set forth above.